The components, such as semiconductor memories, in circuits which are produced using modern microelectronics are becoming ever smaller, and the packing density of the components is becoming ever higher. Furthermore, the charge which is stored in memory components, and which is stored as a data item, is minimal. The data which is stored in the memory components is therefore sensitive to interference. When data is being stored in RAMs, two different types of fault may occur: permanent errors or volatile errors. Permanent errors, which are referred to as hard errors, are caused by defects in the memory ICs themselves or in the drive circuits that are involved. Volatile errors, which are referred to as soft errors, occur only randomly, and are therefore not reproducible. They are caused mainly by alpha radiation. Alpha radiation can reverse the charge of memory capacitors in dynamic RAMS, or else memory flip flops in static RAMS can flip. Volatile errors may also be caused by interference pulses which are produced within or outside the circuit.
The occurrence of memory errors may have far-reaching consequences. For example, a single error in a computer memory can not only cause an incorrect result, but can lead to total failure of the program. In order to avoid such failures and adverse effects, errors such as these must be identified and reported.
One method for error identification is to store one or more checking bits in addition to the data bits. The greater the number of checking bits which are also stored, the more errors can be identified or even corrected.
One procedure for error identification is to transmit a so-called parity bit. This error identification method is referred to as parity checking. Even or odd parities may be agreed. In the case of even parity, the added parity bit is set to zero when the number of ones in the data word is even. The parity bit is set to one when the parity is odd. In consequence, the total number of transmitted ones in a data word including the parity bit is always even. In the case of odd parity, the total number is always odd.
In future technologies, finer structures and the smaller capacitances associated with them will result even more frequently in such soft errors, as mentioned above, in storage circuits. When a parity bit is read, the parity of the data word is recalculated, and is then compared with the parity bit which has likewise been read. If they are the same, the data word has not been changed, and is thus correct. If they are not the same, on the other hand, the data word is incorrect, since at least one bit must have been changed. This procedure, of recalculating the parity on reading and comparing it with the stored value, works for all memories whose data is processed further or assessed only when it is read. However, there are also memory configurations whose contents are read continuously, as is the case by way of example for the coefficients of filter modules in configuration memories. This is likewise the case with memories whose content is searched sporadically, as is done, by way of example, in the case of content-addressable memories (CAMs), which are used as caches.
U.S. Pat. No. 5,434,871 discloses a memory cell arrangement in which continuous parity checking is carried out. The circuit arrangement is designed such that each memory cell is electrically connected to a parity checking circuit. Each parity checking circuit continuously checks the binary memory state of the associated memory cell. The states of the memory cells are joined together in order to make it possible to carry out a parity check for a given data arrangement. Each parity checking circuit has six transistors, in which case, as a result of the design of the parity checking circuit, five transistors are of a first conductance type, and one transistor is of a second conductance type. The parity checking circuit is designed such that one transistor in each case reads the memory state in one of the two memory nodes of the associated memory cell, and these two transistors use a logic EXCLUSIVE-OR operation to link the parity of the associated memory cell to the parity of the previous memory cell. The remaining four transistors in the parity checking circuit are connected such that they transmit to the downstream memory cell the parity result which results from the logic operation, and its complementary parity result. The design of the known parity checking circuit is relatively complex and, owing to the relatively large number (six) of transistors, it requires a relatively high degree of circuit complexity. Furthermore, transistors of both a first and second conductance type are used. This has a considerable disadvantage in the layout design, since separations which are required on the basis of the known rules for CMOS production processes must be complied with and, in the present case, with the required configuration of transistors of a different conductance type, this leads to a considerable space requirement. A further disadvantage of the known parity checking circuit is that, effectively, one diode is used which on average results in a latent parallel current between the supply voltage potential and the ground potential in every alternate memory cell (assuming an equal distribution of logic “0” and “1” states stored in the memory cells) and a constant power loss is produced as a result. Furthermore, one major disadvantage of the known parity checking circuit is that parity checking information must be externally calculated and stored in advance for the parity check. Furthermore, the previous calculation of the parity checking information (parity bit) and the storage of M+1 bits are always used for parity checking, where M indicates the number of bits in a payload data word. This means that the data word length is always used for parity checking. The number of parity checking stages M+1 is thus always greater than the data word length M. This procedure and the fundamental circuit design are highly complex and relatively costly since, inter alia, a relatively large amount of space is required for the circuit.